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March 18, 2008
Intel to Scale Down Nehalem Chip Architecture for Notebooks
On Monday, semiconductor manufacturer Intel announced that its upcoming Nehalem chip microarchitecture, initially designed for servers and high-end desktops, will later be scaled down for notebooks.
According to Macworld UK, the Nehalem architecture will function as a substantial upgrade to Intel's current Core 2 architecture and pack between two and eight cores. Though plans to bring the architecture to notebooks, a company spokesman stated that the company will touch on the subject at the Intel Developer Forum in Shanghai this April.
As far as the design itself is concerned, Intel has stated that each Core in the Nehalem chips will be able to execute two software thread simultaneously, allowing a server to run up to 16 threads at the same time. Each core will have 256 kilobytes of L2 cache and a shared eight megabyte L3 cache while Intel's QuickPath Interconnect technology boosts communication between system components.
The Nehalem architecture will also feature an integrated DDR3 memory controller allowing for up to three times the memory performance of a top of the line Xeon processor. According to company representative Pat Gelsinger, nn optional integrated graphics controller will also be available. The chips are slated for desktop and server release in late 2008 and will be created with a 45 nanometer manufacturing process.
Intel has also stated that it will follow the Nehalem design with the Westmere microarchitecture in 2009 and Sandy Bridge in 2010. The new chips will be manufactured with a 22 nanometer manufacturing process by 2011.
Other upcoming products include work on the Larrabee platform, which will combine multiple cores, threads and graphics capabilities to deliver high speed for the high-performance computing segment, Intel CEO Paul Otellini said at an investor conference in early March. The Larrabee platform may also bundle a graphics processing unit with the CPU on a single chip, Gelsinger said.
For the near term, Intel has also stated that it would ship its first six-core Xeon processor, code-named Dunnington, for the second half of this year. The Dunnington design will be part of Intel's Xeon MP 7300 processor series and will feature a four-processor server with as many as 24 cores. The CPU will feature 1.9 billion transisters and include a 16 megabyte L3 cache.
The lesson here: Invent a time machine to go into the future for the cool stuff, then you can never complain about a faster Mac being released three weeks after you pick up something new.
Let us know what you think over in the comments or forums.
Posted by chrisbarylick at March 18, 2008 8:34 AM
Category: Processors
Tags: 22, 45, Apple, April, chip, DDR3, developer, Forum, Intel, microarchitecture, nanometer, Nehalem, Pat Gelsinger, Paul Otellini, QuickConnect, Sandy Bridge, Westmere
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