Intel Puts 80-core Chip Design Through Its Paces

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Date: Monday, February 12th, 2007, 13:16
Category: News

intellogo.jpg
Macworld News is reporting that Intel researchers are putting an 80-core processor that could perform multiple teraflops (trillions of floating point operations per second) through its paces. The chip design could also use less electricity than a current desktop PC processor.
The processor design fits 80 individual chip cores onto a fingernail-size 275 square millimeter area. According to Jerry Bautista, the director of Intel’s tera-scale research program, the company has no plans to bring the chip to market, but is using it to test high-bandwidth interconnects, revised energy management techniques and new methods of constructing multicore chips.
The design, which currently runs at 3.16 GHz, managed to achieve a 1.01 teraflop rating with an efficiency rating of 16 gigaflops per watt. The chip could have been set to run at a higher speed, but loses efficiency in doing so.
Despite the faster speeds and greatly increased number of cores, the processor is able to save power by placing inactive processor cores into sleep modes, then activating them as needed. The presence of a router built alongside the core allows for a miniature network to be created on the chip. Intel’s engineers have also included memory-based thread scheduling and faster on-chip memory caches to boost the data flow from memory to the processor cores. A layer of “3D stacked memory” located under the chip helps minimize the time, distance and power required to deliver data to the cores.
If you have any comments or feedback, let us know.


intellogo.jpg
Macworld News is reporting that Intel researchers are putting an 80-core processor that could perform multiple teraflops (trillions of floating point operations per second) through its paces. The chip design could also use less electricity than a current desktop PC processor.
The processor design fits 80 individual chip cores onto a fingernail-size 275 square millimeter area. According to Jerry Bautista, the director of Intel’s tera-scale research program, the company has no plans to bring the chip to market, but is using it to test high-bandwidth interconnects, revised energy management techniques and new methods of constructing multicore chips.
The design, which currently runs at 3.16 GHz, managed to achieve a 1.01 teraflop rating with an efficiency rating of 16 gigaflops per watt. The chip could have been set to run at a higher speed, but loses efficiency in doing so.
Despite the faster speeds and greatly increased number of cores, the processor is able to save power by placing inactive processor cores into sleep modes, then activating them as needed. The presence of a router built alongside the core allows for a miniature network to be created on the chip. Intel’s engineers have also included memory-based thread scheduling and faster on-chip memory caches to boost the data flow from memory to the processor cores. A layer of “3D stacked memory” located under the chip helps minimize the time, distance and power required to deliver data to the cores.
If you have any comments or feedback, let us know.

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